Electronic packaging refers to the physical implementations of electrical circuits of integrated circuit (IC) chips, modules, chip or module carriers, cards, boards or backplanes. Such components and devices are often referred to as electronic packaging structures. The terms "electronic packaging structure", "electronic package" and "package" are hereinafter used interchangeably to refer to any or all of the aforementioned devices and structures. For purposes of this discussion, such structures include multilayered packaging, in which a plurality of substantially parallel conductive planes (designated as ground and/or power planes) are separated from one another by non-conductive dielectric material.
It has long been the practice of digital electronic system designers to employ simulation techniques to predict the ultimate behavior of those systems before the actual hardware implementation thereof. As large-scale integration (LSI) and very large-scale integration (VLSI) techniques have allowed greater numbers of circuits to be packaged in smaller spaces, it has become increasingly difficult to construct physical prototypes of proposed digital systems prior to the actual construction of the chip. Therefore, although the simulation of proposed systems was once merely advisable, it is now necessary.
Because of ever-increasing IC transition speed, power/ground noise (known as simultaneous switching noise [SSN] or delta-I noise) has posed a significant challenge to reliable, high-speed IC operation. Numerous problems arising therefrom (such as larger delays, the loss of signal integrity and false switching of devices) can lead to the malfunctioning of overall systems.
SSN or delta-I noise is generated when a logic gate changes state, thereby altering the current flow in a system. The resulting change in current (delta-I) induces transient voltage variations in nearby metallic planes and/or conductors. Of particular interest are voltages induced in the voltage supply and/or ground planes that are usually found in multilayered packages. The effects of noise on actual hardware must be accounted for in any system simulation for the simulation to predict true hardware system performance.
One early attempt to account for delta-I noise is shown in U.S. Pat. No. 4,594,677 (entitled SYSTEM FOR DETECTING AND DIAGNOSING NOISE CAUSED BY SIMULTANEOUS CURRENT SWITCHING) issued to John P. Barlow. Barlow teaches the inclusion of a data file of predetermined delta-I noise "events" which may be integrated with a description of the logic of a digital system to be simulated. The effects of such noise events are then accounted for during the simulation. While an advancement over previous simulation systems, Barlow's system presupposes that a wide variety of relevant delta-I noise events had been accurately captured, events encompassing all possible worst-case scenarios. Since noise events can vary widely from circuit to circuit and, certainly, from package to package, this technique is not suited for the accurate simulation of a wide variety of packages.
Other methods of simulating delta-I noise have focused on modeling the noise-generating mechanisms within the package. Modeling conductive planes using such techniques as lumped, or, effective, inductance are well known in the art. Lumped or effective inductor modeling is valid only at low frequencies; it fails to take into account wave propagation and resonance in power and ground planes. Thus, this technique is unsuitable for modeling high-speed packaging structures.
A technique known as the wire antenna model computes currents in conducting wires using "Method of Moments". The "Method of Moments" is an integral equation method usually formulated in the frequency domain. While this technique is useful for wave propagation effects, the long computation times required for complex multi-layer packaging structures makes it impractical. Another limitation of the wire antenna model is that it computes in the frequency domain; it can, therefore, can not be conveniently linked to time domain circuit simulators.
Yet another technique utilizes a capacitor/inductor mesh to model power and ground planes. For example, this technique is used in the IBM.RTM. ASTAP simulation system. It, too, requires long computation times and the usage of large memory space.
Other high-accuracy techniques employing full-wave electromagnetic field solvers are also available. For example, three-dimensional finite difference time domain (FDTD) or finite elements may be applied. These require quite large computer resources (long computation times, as well as huge memory space), making them impractical for modeling practical package designs.
Numerical techniques have been proposed which take into account wave propagation and resonance effects. These techniques often impose a mesh or a grid to divide the space between planes into small spaces or elements. However, these methods fail to provide consistently accurate simulations of hardware systems due to the complex interactions between a chosen mesh size and critical physical dimensions within a package.